The present disclosure relates to methods of enhancing a thermal anneal of a flash memory in an integrated circuit (IC) chip package by addition of an electric field. Specifically, the present disclosure relates to a method of recovering a voltage threshold of a flash memory cell that has undergone many program/erase (P/E) cycles by simultaneously heating and applying an electric field to a tunnel dielectric layer of the flash memory cell, to release charge trapped within the tunnel dielectric layer, effecting a field effect transistor threshold voltage shift.
Flash memory is a class of non-volatile integrated circuit memory technology. Referring to FIG. 1, a flash memory cell 100 comprises a field effect transistor (FET) having a source 102 and drain 104 separated by a channel 105 in a doped silicon substrate 101, and two gates 107, 109. A metal layer 110 that connects the various flash memory cells is disposed distally to the control gate 109, relative to the silicon substrate 101. A control gate 109 is separated from the channel 105 by a blocking dielectric layer 108, a floating gate 107, and a tunnel dielectric layer 106. The floating gate 107 may comprise polysilicon that is completely isolated by the silicon oxides of the blocking dielectric layer 108 and the tunnel dielectric layer 106. Alternatively, the floating gate 107 may form a charge storage layer in a SONOS device, where the source 102, drain 104, and channel 105 are formed in a silicon substrate (S) 101, the tunnel dielectric layer 106 is formed of silicon oxide (0), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer 108 is formed of silicon oxide (0), and the control gate 109 is formed of polysilicon (S).
A flash memory cell uses the floating gate or charge storage layer to store an information bit, according to the presence or absence of charge. If the floating gate or charge storage layer is not charged, then the device operates like a FET, i.e., a positive charge in the control gate creates a channel in a p-type doped silicon substrate that carries current from the source to the drain. If, however, the floating gate or charge storage layer is negatively charged, then this charge shields the channel region from the electric field of the control gate and inhibits the formation of a channel between the source and drain. The threshold voltage is the voltage applied to the control gate at which the transistor becomes conductive. The presence or absence of a negative charge on the floating gate or charge storage layer results in a more positive or negative threshold voltage, respectively.
In flash memory, programming a flash memory cell requires putting electrons onto the floating gate or charge storage layer, which is associated with a bit value of 0, while erasing or removing electrons from the floating gate or charge storage layer results in re-setting the flash memory cell to a bit value of 1. Typically, the tunnel dielectric layer of a flash memory cell is impermeable to low energy electrons, but can pass high-energy electrons.
To effect programming of a flash memory cell, channel hot electron (CHE) injection applies a lower positive voltage to the drain of a p-type doped semiconductor substrate to activate “hot electrons” in the channel, respective to the grounded source, and then also applies a higher positive voltage to the control gate, to attract the “hot electrons” to the floating gate or charge storage layer through the tunnel dielectric layer. Erasing a flash memory cell requires application of a large negative voltage, e.g., −15V, between the control gate and the grounded source of the p-type doped semiconductor substrate or the grounded substrate, itself, to pull electrons from the floating gate or charge storage layer by quantum tunneling through the tunnel dielectric to the grounded source or semiconductor substrate. Typically, erasing can only be performed on a block-wise basis, i.e., all the flash memory cells of an addressable block of flash memory cells are erased together.
Fowler-Nordheim (F-N) tunneling is a quantum-mechanical process whereby a particle, e.g., an electron, can pass through a classically forbidden region such as the tunnel dielectric layer of the flash memory cell. To use the Fowler-Nordheim effect, a strong electric field must be applied across the forbidden region. In a flash memory cell, the increased strength of the electric field applied across the tunnel dielectric layer may be achieved by using a relatively thin dielectric layer with a voltage of, for example, 5-20 V, where electric field strength is measured in volts per meter. When the applied voltage of the control gate is positive to that of the doped silicon substrate, electrons may move from the silicon substrate through the thin layer of the tunnel dielectric into the floating gate or charge storage layer to program the flash memory cell.
Due to the strong electric fields used in program/erase (P/E) cycles of flash memory, the tunnel dielectric layer beneath the floating gate or charge storage layer may become degraded over time. It is well known that charge traps are created in oxides of the dielectric leading to a reduction of endurance capacity and data retention time in a flash memory chip. This limitation to flash memory chips, i.e., charge trapping caused by multiple P/E cycles, is typically measured by a shift in the threshold voltage over a number of P/E cycles. Currently, manufacturers specify for their flash memory chips, a threshold voltage shift per 100,000 P/E cycles, which permits nominal operation.
Until recently, attempts to cure the shift in threshold voltage over multiple P/E cycles by annealing flash memory chips were regarded as impractical because the entire memory chip would need heating for hours at around 250° C. However, by redesigning the flash memory chips to include onboard heaters that heat restricted areas of the flash memory chip with a brief pulse of heat, i.e., about 800° C., the flash memory chip can return to a “good” state.
There remains a need to realize the benefits of annealing a flash memory chip at a modest elevated temperature to integrated circuits in the field.